A Hardware Efficient Preamble Detection Algorithm for Powerline Communication

Orthogonal frequency-division multiplexing (OFDM) systems are widely used in today’s packet based communication systems such as wireless and powerline communications. The latter is of increasing interest for the use in smart grid applications or Internet of things (IoT). Some of the OFDM systems use a preamble preceding to the transmitted packet header and data to perform time and frequency synchronization. Common approaches for the detection of this preamble are using the cyclic repetition of repeated preambles or the cross-correlation of the transmitted and the reference preamble. While providing good performance in low signal-to-noise-ratio (SNR) channels the cross-correlation is a very costly operation when it is implemented in hardware. The field of application for the powerline system is an environment featuring a very low SNR channel. Therefore, the cross-correlation based preamble detection is chosen. To reduce the hardware size the effect of quantization on the cross-correlation is evaluated and a new side-lobe correlation algorithm (SLC) is introduced. The results of simulation show an improvement of up to 5 dB in SNR for various single and multipath channels. The FPGA implementation results of the SLC algorithm demonstrate that the required hardware effort can be significantly reduced by a factor of three, while providing the same minimum SNR.