Alternative approaches implementing high-performance FIR filters on lookup table-based FPGAs: A comparison

Finite impulse response filters (FIR filters) are very commonly used in digital signal processing (DSP) applications and are traditionally implemented using ASICs or DSP-processors. For FPGA implementation, due to the high throughput rate and large computational power required under real-time constraints, they are a challenging subject. Indeed, the limitation of resources on FPGA, i.e., logic blocks and flip flops, and furthermore, the high routing delays, requires compact implementations of the circuits. Three approaches for implementation of high-performance symmetric FIR filters on lookup table-based FPGAs will be considered in this paper: Fully parallel distributed arithmetic, table lookup multiplication, and conventional hardware multiplication. Implementation results will be illustrated by an 8 taps 8 bits symmetric FIR filter, and comparative considerations of the above approaches invoked for Xilinx FPGAs will be also shown.