Abstract
This work introduces a full custom RISC-V processor specifically targeted for harsh environments capable of
sustained operation at 180 MHz while withstanding temperatures up to 175°C. Built using a state-of-the-art
180nm silicon-on-insulator (SOI) technology, the processor overcomes the limitations of existing designs, such as
increased leakage currents and reduced carrier mobility in extreme environments. Key innovations include a
deeply pipelined architecture optimized for thermal stability, modular execution pipelines to handle high-latency
operations without stalling, and tightly coupled caches using single-port SRAM with custom wrappers for high
throughput. In contrast to other well known architectures for harsh environments, which usually target radiation
resistance in space, this design is tailored specifically for high-temperature resilience. Extensive testing validated
its performance and reliability.
sustained operation at 180 MHz while withstanding temperatures up to 175°C. Built using a state-of-the-art
180nm silicon-on-insulator (SOI) technology, the processor overcomes the limitations of existing designs, such as
increased leakage currents and reduced carrier mobility in extreme environments. Key innovations include a
deeply pipelined architecture optimized for thermal stability, modular execution pipelines to handle high-latency
operations without stalling, and tightly coupled caches using single-port SRAM with custom wrappers for high
throughput. In contrast to other well known architectures for harsh environments, which usually target radiation
resistance in space, this design is tailored specifically for high-temperature resilience. Extensive testing validated
its performance and reliability.
| Originalsprache | Englisch |
|---|---|
| Seiten | 1-2 |
| Seitenumfang | 2 |
| Publikationsstatus | Veröffentlicht - 29 Juli 2025 |
| Veranstaltung | RISC-V Summit 2025 Europe - Cité des sciences et de l'industrie, Paris, Frankreich Dauer: 12 Mai 2025 → 15 Mai 2025 https://riscv-europe.org/summit/2025/ |
Konferenz
| Konferenz | RISC-V Summit 2025 Europe |
|---|---|
| Land/Gebiet | Frankreich |
| Ort | Paris |
| Zeitraum | 12 Mai 2025 → 15 Mai 2025 |
| Internetadresse |
Schlagwörter
- RISC-V
- ASIP
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