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High Performance RISC-V Processor for Application in Harsh Environments

Malte Hawich, Malte Rücker, Tobias Stuckenberg, Holger Christoph Blume

Publikation: KonferenzbeitragPaperForschungPeer-Review

Abstract

This work introduces a full custom RISC-V processor specifically targeted for harsh environments capable of
sustained operation at 180 MHz while withstanding temperatures up to 175°C. Built using a state-of-the-art
180nm silicon-on-insulator (SOI) technology, the processor overcomes the limitations of existing designs, such as
increased leakage currents and reduced carrier mobility in extreme environments. Key innovations include a
deeply pipelined architecture optimized for thermal stability, modular execution pipelines to handle high-latency
operations without stalling, and tightly coupled caches using single-port SRAM with custom wrappers for high
throughput. In contrast to other well known architectures for harsh environments, which usually target radiation
resistance in space, this design is tailored specifically for high-temperature resilience. Extensive testing validated
its performance and reliability.
OriginalspracheEnglisch
Seiten1-2
Seitenumfang2
PublikationsstatusVeröffentlicht - 29 Juli 2025
VeranstaltungRISC-V Summit 2025 Europe - Cité des sciences et de l'industrie, Paris, Frankreich
Dauer: 12 Mai 202515 Mai 2025
https://riscv-europe.org/summit/2025/

Konferenz

KonferenzRISC-V Summit 2025 Europe
Land/GebietFrankreich
OrtParis
Zeitraum12 Mai 202515 Mai 2025
Internetadresse

Schlagwörter

  • RISC-V
  • ASIP

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