Memory organization of a single-chip video signal processing system with embedded DRAM

Joerg Hilgenstock; Klaus Herrmann; Peter Pirsch

Memory organization of a single-chip video signal processing system with embedded DRAM

Joerg Hilgenstock^*
, Klaus Herrmann
, Peter Pirsch

^*Korrespondierende*r Autor*in für diese Arbeit

Publikation: Beitrag in Buch/Bericht/Sammelwerk/Konferenzband › Aufsatz in Konferenzband › Forschung › Peer-Review

Abstract

A programmable single-chip multiprocessor system for video coding applications has been developed. It integrates four processing elements, on-chip DRAM, and application-specific interfaces. The integrated DRAM is primarily used as frame buffer and makes external memory for most applications obsolete. For fast access to local data segments also static RAM is integrated in each processing element.

Originalsprache	Englisch
Titel des Sammelwerks	Proceedings of the IEEE Great Lakes Symposium on VLSI
Herausgeber (Verlag)	IEEE
Seiten	42-45
Seitenumfang	4
ISBN (Print)	0769501044
Publikationsstatus	Veröffentlicht - 1999
Veranstaltung	1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99) - Ann Arbor, MI, USA Dauer: 4 März 1999 → 6 März 1999

Publikationsreihe

Name	Proceedings of the IEEE Great Lakes Symposium on VLSI
ISSN (Print)	1066-1395

Konferenz

Konferenz	1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99)
Ort	Ann Arbor, MI, USA
Zeitraum	4 März 1999 → 6 März 1999

ASJC Scopus Sachgebiete

Elektrotechnik und Elektronik

Andere Dateien und Links

Verknüpfung zur Publikation in Scopus

Dieses zitieren

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title = "Memory organization of a single-chip video signal processing system with embedded DRAM",

abstract = "A programmable single-chip multiprocessor system for video coding applications has been developed. It integrates four processing elements, on-chip DRAM, and application-specific interfaces. The integrated DRAM is primarily used as frame buffer and makes external memory for most applications obsolete. For fast access to local data segments also static RAM is integrated in each processing element.",

author = "Joerg Hilgenstock and Klaus Herrmann and Peter Pirsch",

year = "1999",

language = "English",

isbn = "0769501044",

series = "Proceedings of the IEEE Great Lakes Symposium on VLSI",

publisher = "IEEE",

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note = "1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99) ; Conference date: 04-03-1999 Through 06-03-1999",

}

Memory organization of a single-chip video signal processing system with embedded DRAM. / Hilgenstock, Joerg; Herrmann, Klaus; Pirsch, Peter.
Proceedings of the IEEE Great Lakes Symposium on VLSI. IEEE, 1999. S. 42-45 (Proceedings of the IEEE Great Lakes Symposium on VLSI).

Publikation: Beitrag in Buch/Bericht/Sammelwerk/Konferenzband › Aufsatz in Konferenzband › Forschung › Peer-Review

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AU - Pirsch, Peter

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AB - A programmable single-chip multiprocessor system for video coding applications has been developed. It integrates four processing elements, on-chip DRAM, and application-specific interfaces. The integrated DRAM is primarily used as frame buffer and makes external memory for most applications obsolete. For fast access to local data segments also static RAM is integrated in each processing element.

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T3 - Proceedings of the IEEE Great Lakes Symposium on VLSI

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