A Hardware Efficient Digital DAC Linearization Topology for Delta-Sigma ADCs

This paper presents a digital topology for linearizing multi-bit feedback digital-to-analog converters (DACs) in delta-sigma modulators (Δ Σ Ms). The proposed topology significantly surpasses existing techniques in hardware utilization, efficiency, and implementation effort by simplifying the complex digital transfer functions in the digital linearization system to a gain-only transfer function and by sparing an explicit adder for the mismatch correction. These simplifications still allow an almost ideal linearization of the overall system, improving our exemplary Δ Σ M by more than 30dB in spurious free dynamic range (SFDR) as well as 33dB in signal to noise and distortion ratio (SNDR). Furthermore, the technique's hardware utilization is reduced by almost 50% compared to techniques utilizing complex transfer functions for the digital linearization. The presented linearization topology offers a practical and efficient solution for high-bandwidth systems reducing the implementation effort as well as the power consumption.