A Low-Distortion Adderless Zero-Time Reset Incremental Delta-Sigma Analog-to-Digital Converter

This work presents a low-distortion adderless switched-capacitor (SC) incremental delta-sigma modulator (I-Δ Σ M), where the reset in the SC circuit is applied for half a cycle, thereby achieving a zero-time reset from a system perspective. It is derived that the adderless low-distortion path is maintained as it effectively becomes an SC-adder path directly following the reset. The key innovation of this work lies in the combination of the adderless topology with the zero-time reset, along with the derivation of the inherently higher bandwidth of a half cycle reset system. In contrast to state-of-the-art (SOTA) I-Δ Σ M designs, which predominantly implement a full cycle reset, the zero-time reset yields valuable bandwidth. By means of a 2nd-order architecture, it is shown that the bandwidth increases by 12.5% at an oversampling ratio (OSR) of 8, while achieving nearly identical resolution. The concept is verified by simulation in a 55 nm CMOS technology. It is shown that neither the transmission gates nor limitations in the amplifiers impede the settling of the reset, which proves that the zero-time reset can be implemented in most SC-I- Δ Σ Ms designs to increase the bandwidth.