ASIP-eFPGA Architecture for Multioperable GNSS Receivers

Thorsten Von Sydow; Holger Blume; Götz Kappen; Tobias G. Noll

doi:10.1007/978-3-540-70550-5_15

ASIP-eFPGA Architecture for Multioperable GNSS Receivers

Thorsten Von Sydow^*, Holger Blume, Götz Kappen, Tobias G. Noll

^*Corresponding author for this work

RWTH Aachen University

Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review

Abstract

In this paper a novel flexible architecture exemplarily applied for multioperable GNSS receivers including an ASIP and an arithmetic oriented embedded FPGA is presented. The advent of next generation GNSS-systems as well as different demands in different system phases require high flexibility. The proposed architecture provides high energy and area efficiency compared to software-programmable processor while preserving flexibility. Exemplarily the mapping of the computational intensive base band processing of a Navstar GPS receiver to an ASIP-eFPGA architecture will be discussed. Results are based on a standard cell based design regarding the ASIP. A design method for physically optimized VLSI-macros has been applied for the implementation of the eFPGA. All results are acquired for a 90 nm-CMOS technology. It will be shown that the proposed heterogeneous architecture features an attractive position in the design space regarding area and energy efficiency as well as flexibility.

Original language	English
Title of host publication	Embedded Computer Systems
Subtitle of host publication	Architectures, Modeling, and Simulation - 8th International Workshop, SAMOS 2008, Proceedings
Editors	M. Bereković, N. Dimopoulos, S. Wong
Publisher	Springer Verlag
Pages	136-145
Number of pages	10
ISBN (Electronic)	978-3-540-70550-5
ISBN (Print)	354070549X, 9783540705499
DOIs	https://doi.org/10.1007/978-3-540-70550-5_15
Publication status	Published - 2008
Externally published	Yes
Event	8th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2008 - Samos, Greece Duration: 21 Jul 2008 → 24 Jul 2008

Publication series

Name	Lecture Notes in Computer Science (LNCS)
Volume	5114
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

Conference

Conference	8th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2008
Country/Territory	Greece
City	Samos
Period	21 Jul 2008 → 24 Jul 2008

UN Sustainable Development Goals (SDGs)

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

Arithmetic oriented eFPGA
ASIP
Multioperable GNSS

ASJC Scopus subject areas

Theoretical Computer Science
General Computer Science

Access to Document

10.1007/978-3-540-70550-5_15

Cite this

Von Sydow, T., Blume, H., Kappen, G., & Noll, T. G. (2008). ASIP-eFPGA Architecture for Multioperable GNSS Receivers. In M. Bereković, N. Dimopoulos, & S. Wong (Eds.), Embedded Computer Systems: Architectures, Modeling, and Simulation - 8th International Workshop, SAMOS 2008, Proceedings (pp. 136-145). (Lecture Notes in Computer Science (LNCS); Vol. 5114). Springer Verlag. https://doi.org/10.1007/978-3-540-70550-5_15

Von Sydow, Thorsten ; Blume, Holger ; Kappen, Götz et al. / ASIP-eFPGA Architecture for Multioperable GNSS Receivers. Embedded Computer Systems: Architectures, Modeling, and Simulation - 8th International Workshop, SAMOS 2008, Proceedings. editor / M. Bereković ; N. Dimopoulos ; S. Wong. Springer Verlag, 2008. pp. 136-145 (Lecture Notes in Computer Science (LNCS)).

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title = "ASIP-eFPGA Architecture for Multioperable GNSS Receivers",

abstract = "In this paper a novel flexible architecture exemplarily applied for multioperable GNSS receivers including an ASIP and an arithmetic oriented embedded FPGA is presented. The advent of next generation GNSS-systems as well as different demands in different system phases require high flexibility. The proposed architecture provides high energy and area efficiency compared to software-programmable processor while preserving flexibility. Exemplarily the mapping of the computational intensive base band processing of a Navstar GPS receiver to an ASIP-eFPGA architecture will be discussed. Results are based on a standard cell based design regarding the ASIP. A design method for physically optimized VLSI-macros has been applied for the implementation of the eFPGA. All results are acquired for a 90 nm-CMOS technology. It will be shown that the proposed heterogeneous architecture features an attractive position in the design space regarding area and energy efficiency as well as flexibility.",

keywords = "Arithmetic oriented eFPGA, ASIP, Multioperable GNSS",

author = "{Von Sydow}, Thorsten and Holger Blume and G{\"o}tz Kappen and Noll, {Tobias G.}",

year = "2008",

doi = "10.1007/978-3-540-70550-5_15",

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isbn = "354070549X",

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Von Sydow, T, Blume, H, Kappen, G & Noll, TG 2008, ASIP-eFPGA Architecture for Multioperable GNSS Receivers. in M Bereković, N Dimopoulos & S Wong (eds), Embedded Computer Systems: Architectures, Modeling, and Simulation - 8th International Workshop, SAMOS 2008, Proceedings. Lecture Notes in Computer Science (LNCS), vol. 5114, Springer Verlag, pp. 136-145, 8th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2008, Samos, Greece, 21 Jul 2008. https://doi.org/10.1007/978-3-540-70550-5_15

ASIP-eFPGA Architecture for Multioperable GNSS Receivers. / Von Sydow, Thorsten; Blume, Holger; Kappen, Götz et al.
Embedded Computer Systems: Architectures, Modeling, and Simulation - 8th International Workshop, SAMOS 2008, Proceedings. ed. / M. Bereković; N. Dimopoulos; S. Wong. Springer Verlag, 2008. p. 136-145 (Lecture Notes in Computer Science (LNCS); Vol. 5114).

Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review

TY - GEN

T1 - ASIP-eFPGA Architecture for Multioperable GNSS Receivers

AU - Von Sydow, Thorsten

AU - Blume, Holger

AU - Kappen, Götz

AU - Noll, Tobias G.

PY - 2008

Y1 - 2008

N2 - In this paper a novel flexible architecture exemplarily applied for multioperable GNSS receivers including an ASIP and an arithmetic oriented embedded FPGA is presented. The advent of next generation GNSS-systems as well as different demands in different system phases require high flexibility. The proposed architecture provides high energy and area efficiency compared to software-programmable processor while preserving flexibility. Exemplarily the mapping of the computational intensive base band processing of a Navstar GPS receiver to an ASIP-eFPGA architecture will be discussed. Results are based on a standard cell based design regarding the ASIP. A design method for physically optimized VLSI-macros has been applied for the implementation of the eFPGA. All results are acquired for a 90 nm-CMOS technology. It will be shown that the proposed heterogeneous architecture features an attractive position in the design space regarding area and energy efficiency as well as flexibility.

AB - In this paper a novel flexible architecture exemplarily applied for multioperable GNSS receivers including an ASIP and an arithmetic oriented embedded FPGA is presented. The advent of next generation GNSS-systems as well as different demands in different system phases require high flexibility. The proposed architecture provides high energy and area efficiency compared to software-programmable processor while preserving flexibility. Exemplarily the mapping of the computational intensive base band processing of a Navstar GPS receiver to an ASIP-eFPGA architecture will be discussed. Results are based on a standard cell based design regarding the ASIP. A design method for physically optimized VLSI-macros has been applied for the implementation of the eFPGA. All results are acquired for a 90 nm-CMOS technology. It will be shown that the proposed heterogeneous architecture features an attractive position in the design space regarding area and energy efficiency as well as flexibility.

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SN - 354070549X

SN - 9783540705499

T3 - Lecture Notes in Computer Science (LNCS)

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A2 - Dimopoulos, N.

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T2 - 8th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2008

Y2 - 21 July 2008 through 24 July 2008

ER -

Von Sydow T, Blume H, Kappen G, Noll TG. ASIP-eFPGA Architecture for Multioperable GNSS Receivers. In Bereković M, Dimopoulos N, Wong S, editors, Embedded Computer Systems: Architectures, Modeling, and Simulation - 8th International Workshop, SAMOS 2008, Proceedings. Springer Verlag. 2008. p. 136-145. (Lecture Notes in Computer Science (LNCS)). doi: 10.1007/978-3-540-70550-5_15

ASIP-eFPGA Architecture for Multioperable GNSS Receivers

Abstract

Publication series

Conference

UN Sustainable Development Goals (SDGs)

Keywords

ASJC Scopus subject areas

Access to Document

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Cite this