Memory organization of a single-chip video signal processing system with embedded DRAM

Joerg Hilgenstock; Klaus Herrmann; Peter Pirsch

Memory organization of a single-chip video signal processing system with embedded DRAM

Joerg Hilgenstock^*
, Klaus Herrmann
, Peter Pirsch

^*Corresponding author for this work

Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review

Abstract

A programmable single-chip multiprocessor system for video coding applications has been developed. It integrates four processing elements, on-chip DRAM, and application-specific interfaces. The integrated DRAM is primarily used as frame buffer and makes external memory for most applications obsolete. For fast access to local data segments also static RAM is integrated in each processing element.

Original language	English
Title of host publication	Proceedings of the IEEE Great Lakes Symposium on VLSI
Publisher	IEEE
Pages	42-45
Number of pages	4
ISBN (Print)	0769501044
Publication status	Published - 1999
Event	1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99) - Ann Arbor, MI, USA Duration: 4 Mar 1999 → 6 Mar 1999

Publication series

Name	Proceedings of the IEEE Great Lakes Symposium on VLSI
ISSN (Print)	1066-1395

Conference

Conference	1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99)
City	Ann Arbor, MI, USA
Period	4 Mar 1999 → 6 Mar 1999

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

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title = "Memory organization of a single-chip video signal processing system with embedded DRAM",

abstract = "A programmable single-chip multiprocessor system for video coding applications has been developed. It integrates four processing elements, on-chip DRAM, and application-specific interfaces. The integrated DRAM is primarily used as frame buffer and makes external memory for most applications obsolete. For fast access to local data segments also static RAM is integrated in each processing element.",

author = "Joerg Hilgenstock and Klaus Herrmann and Peter Pirsch",

year = "1999",

language = "English",

isbn = "0769501044",

series = "Proceedings of the IEEE Great Lakes Symposium on VLSI",

publisher = "IEEE",

pages = "42--45",

booktitle = "Proceedings of the IEEE Great Lakes Symposium on VLSI",

note = "1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99) ; Conference date: 04-03-1999 Through 06-03-1999",

}

Memory organization of a single-chip video signal processing system with embedded DRAM. / Hilgenstock, Joerg; Herrmann, Klaus; Pirsch, Peter.
Proceedings of the IEEE Great Lakes Symposium on VLSI. IEEE, 1999. p. 42-45 (Proceedings of the IEEE Great Lakes Symposium on VLSI).

Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review

TY - GEN

T1 - Memory organization of a single-chip video signal processing system with embedded DRAM

AU - Hilgenstock, Joerg

AU - Herrmann, Klaus

AU - Pirsch, Peter

PY - 1999

Y1 - 1999

N2 - A programmable single-chip multiprocessor system for video coding applications has been developed. It integrates four processing elements, on-chip DRAM, and application-specific interfaces. The integrated DRAM is primarily used as frame buffer and makes external memory for most applications obsolete. For fast access to local data segments also static RAM is integrated in each processing element.

AB - A programmable single-chip multiprocessor system for video coding applications has been developed. It integrates four processing elements, on-chip DRAM, and application-specific interfaces. The integrated DRAM is primarily used as frame buffer and makes external memory for most applications obsolete. For fast access to local data segments also static RAM is integrated in each processing element.

UR - https://www.scopus.com/pages/publications/0033361601

M3 - Conference contribution

AN - SCOPUS:0033361601

SN - 0769501044

T3 - Proceedings of the IEEE Great Lakes Symposium on VLSI

SP - 42

EP - 45

BT - Proceedings of the IEEE Great Lakes Symposium on VLSI

PB - IEEE

T2 - 1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99)

Y2 - 4 March 1999 through 6 March 1999

ER -

Memory organization of a single-chip video signal processing system with embedded DRAM

Abstract

Publication series

Conference

ASJC Scopus subject areas

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Cite this