Yield and speed optimization of a latch-type voltage sense amplifier

Bernhard Wicht; Thomas Nirschl; Doris Schmitt-Landsiedel

doi:10.1109/JSSC.2004.829399

Yield and speed optimization of a latch-type voltage sense amplifier

Bernhard Wicht^*
, Thomas Nirschl
, Doris Schmitt-Landsiedel

^*Corresponding author for this work

Research output: Contribution to journal › Article › Research › peer review

Abstract

A quantitative yield analysis of a latch-type voltage sense amplifier with a high-impedance differential input stage is presented. It investigates the impact of supply voltage, input dc level, transistor sizing, and temperature on the input offset voltage. The input dc level turns out to be most significant. Also, an analytical expression for the sensing delay is derived which shows low sensitivity on the input dc bias voltage. A figure of merit indicates that an input dc level of 0.7 V_DD is optimal regarding speed and yield. Experimental results in 130-nm CMOS technology confirm that the yield can be significantly improved by lowering the input dc voltage to about 70% of the supply voltage. Thereby, the offset standard deviation decreases from 19 to 8.5 mV without affecting the delay.

Original language	English
Pages (from-to)	1148-1158
Number of pages	11
Journal	IEEE Journal of Solid-State Circuits
Volume	39
Issue number	7
DOIs	https://doi.org/10.1109/JSSC.2004.829399
Publication status	Published - Jul 2004
Externally published	Yes

Keywords

Current sensing
Latch delay
Latch-type sense amplifier
Sense amplifier
SRAM circuits
SRAM yield
Yield optimization

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/JSSC.2004.829399

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title = "Yield and speed optimization of a latch-type voltage sense amplifier",

abstract = "A quantitative yield analysis of a latch-type voltage sense amplifier with a high-impedance differential input stage is presented. It investigates the impact of supply voltage, input dc level, transistor sizing, and temperature on the input offset voltage. The input dc level turns out to be most significant. Also, an analytical expression for the sensing delay is derived which shows low sensitivity on the input dc bias voltage. A figure of merit indicates that an input dc level of 0.7 VDD is optimal regarding speed and yield. Experimental results in 130-nm CMOS technology confirm that the yield can be significantly improved by lowering the input dc voltage to about 70\% of the supply voltage. Thereby, the offset standard deviation decreases from 19 to 8.5 mV without affecting the delay.",

keywords = "Current sensing, Latch delay, Latch-type sense amplifier, Sense amplifier, SRAM circuits, SRAM yield, Yield optimization",

author = "Bernhard Wicht and Thomas Nirschl and Doris Schmitt-Landsiedel",

year = "2004",

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doi = "10.1109/JSSC.2004.829399",

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pages = "1148--1158",

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T1 - Yield and speed optimization of a latch-type voltage sense amplifier

AU - Wicht, Bernhard

AU - Nirschl, Thomas

AU - Schmitt-Landsiedel, Doris

PY - 2004/7

Y1 - 2004/7

N2 - A quantitative yield analysis of a latch-type voltage sense amplifier with a high-impedance differential input stage is presented. It investigates the impact of supply voltage, input dc level, transistor sizing, and temperature on the input offset voltage. The input dc level turns out to be most significant. Also, an analytical expression for the sensing delay is derived which shows low sensitivity on the input dc bias voltage. A figure of merit indicates that an input dc level of 0.7 VDD is optimal regarding speed and yield. Experimental results in 130-nm CMOS technology confirm that the yield can be significantly improved by lowering the input dc voltage to about 70% of the supply voltage. Thereby, the offset standard deviation decreases from 19 to 8.5 mV without affecting the delay.

AB - A quantitative yield analysis of a latch-type voltage sense amplifier with a high-impedance differential input stage is presented. It investigates the impact of supply voltage, input dc level, transistor sizing, and temperature on the input offset voltage. The input dc level turns out to be most significant. Also, an analytical expression for the sensing delay is derived which shows low sensitivity on the input dc bias voltage. A figure of merit indicates that an input dc level of 0.7 VDD is optimal regarding speed and yield. Experimental results in 130-nm CMOS technology confirm that the yield can be significantly improved by lowering the input dc voltage to about 70% of the supply voltage. Thereby, the offset standard deviation decreases from 19 to 8.5 mV without affecting the delay.

KW - Current sensing

KW - Latch delay

KW - Latch-type sense amplifier

KW - Sense amplifier

KW - SRAM circuits

KW - SRAM yield

KW - Yield optimization

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DO - 10.1109/JSSC.2004.829399

M3 - Article

AN - SCOPUS:3042778488

SN - 0018-9200

VL - 39

SP - 1148

EP - 1158

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 7

ER -

Yield and speed optimization of a latch-type voltage sense amplifier

Abstract

Keywords

ASJC Scopus subject areas

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