TY - JOUR
T1 - ZuSE-KI-Mobil
T2 - AI Chip Design Platform for Automotive and Industrial Applications
AU - Mojumder, Shaown
AU - Friedrich, Simon
AU - Matúš, Emil
AU - Lüders, Matthias
AU - Friedrich, Martin
AU - Renke, Oliver
AU - Blume, Holger
AU - Kock, Markus
AU - Schewior, Gregor
AU - Grantz, Darius
AU - Benndorf, Jens
AU - Hoefer, Julian
AU - Schmidt, Patrick
AU - Becker, Jürgen
AU - Fasfous, Nael
AU - Mori, Pierpaolo
AU - Vögel, Hans Jörg
AU - Ahmadifarsani, Samira
AU - Kontopoulos, Leonidas
AU - Schlichtmann, Ulf
AU - Li, Yun Jin
AU - Fettweis, Gerhard P.
N1 - Publisher Copyright:
© 1993-2012 IEEE.
PY - 2025/10/31
Y1 - 2025/10/31
N2 - The ZuSE-KI-Mobil (ZuKIMo) research project presents a heterogeneous system-on-chip (SoC) designed for use in a variety of automotive and industrial edge applications. Implemented using GlobalFoundries (GF) 22-nm FD-SOI technology, the SoC features a modular architecture with a configurable, bit-serial, mixed-precision neural processing unit (NPU) core. This core can be adapted to different use cases, comes with a compact instruction set, and improves the performance of dilated convolutions. A hardware-accelerated, tunable image signal processor (ISP) hyperparameter pipeline reduces tuning time and increases detection confidence for AI tasks. The system also incorporates a selective, per-layer fault-tolerance mechanism and supports rapid prototyping via an Apache TVM-driven compiler flow and cycle-accurate simulation. The adaptable hardware generation process is designed with future chiplet-based scaling in mind, providing a flexible foundation for upcoming heterogeneous SoC designs.
AB - The ZuSE-KI-Mobil (ZuKIMo) research project presents a heterogeneous system-on-chip (SoC) designed for use in a variety of automotive and industrial edge applications. Implemented using GlobalFoundries (GF) 22-nm FD-SOI technology, the SoC features a modular architecture with a configurable, bit-serial, mixed-precision neural processing unit (NPU) core. This core can be adapted to different use cases, comes with a compact instruction set, and improves the performance of dilated convolutions. A hardware-accelerated, tunable image signal processor (ISP) hyperparameter pipeline reduces tuning time and increases detection confidence for AI tasks. The system also incorporates a selective, per-layer fault-tolerance mechanism and supports rapid prototyping via an Apache TVM-driven compiler flow and cycle-accurate simulation. The adaptable hardware generation process is designed with future chiplet-based scaling in mind, providing a flexible foundation for upcoming heterogeneous SoC designs.
KW - AI accelerator
KW - autonomous systems
KW - compiler
KW - edge computing
KW - system-on-chip (SoC)
UR - https://www.scopus.com/pages/publications/105016243712
U2 - 10.1109/TVLSI.2025.3603887
DO - 10.1109/TVLSI.2025.3603887
M3 - Article
AN - SCOPUS:105016243712
SN - 1063-8210
VL - 33
SP - 2961
EP - 2974
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 11
ER -